During a recent look at ActiveDesign product from Jasper (http://www.jasper-da.com/products/ActiveDesign.htm), I was pleasantly surprised to see a high quality design being used as the case study. Usually such early product demos contain tightly canned examples, showing only the relevant tool features and much less on the actual design. Here is a refresher – we get a very representative real life design – AHB-lite to AXI bridge with 4 AHB-lite masters, a refreshing change in EDA space.
See below for a screenshot of the demo design:
Tool demos are not on dummy designs, becoming more and more realistic indeed!
On a similar note, Breker’s Trek (www.brekersystems.com) has $TREK_HOME/examples that are complete SoC level test synthesis – not just “Hello World”, “foo-bar” anymore! Other interesting designs include a Cache controller model, CPU etc.
Similar is the SoC kit initiative from Cadence (www.cadence.com/products/fv/iv_kit) – this one tops the list of all EDA demos I’ve seen in years on Verification – they started back in late 2007 and have been growing in strength over years. During CDNLive 09 @ Bangalore, CDN showed their roadmap for these kits and clear indications are that these will be extended to ESL platforms too.
Sure all vendors ship more and more examples with their tools nowadays, this also means they employ/engage with real verification engineers besides R&D, support engineers, good for the job market, hopefully :-)
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