Random testing for VHDL based designs

With so much buzz around CRV (Constrained Random Verification) it is hard to imagine that VHDL based design teams are staying quite away from this approach. From our experience at CVC, we have seen that SV-Tesbench with VHDL DUT is not that hard to get it working, so excpet for some additional tool cost (mabye?) it is very much a feaisble approach. However with great push and dedication from Jim Lewis, we are seeing that VHDL is fast catching up. See recent Aldec seminar for instance: http://www.aldec.com/Events/Event.aspx?companyeventid=74

Implementing Constrained Random Verification with VHDL

Interesting...